Higher-level representations (macromodels, reduced-order models) abstract away unnecessary implementation details and model only important system properties such as functionality. This methodology -- well-developed for linear systems and digital (Boolean) circuits -- is not mature for general nonlinear systems (such as analog/mixed-signal circuits). Questions arise regarding abstracting/macromodeling nonlinear dynamical systems: What are ``important'' system properties to preserve in the macromodel? What is the appropriate representation of the macromodel? What is the general algorithmic framework to develop a macromodel? How to automatically derive a macromodel from a white-box/black-box model. This dissertation presents techniques for solving the problem of macromodeling nonlinear dynamical systems by trying to answer these questions. We formulate the nonlinear model order reduction problem as an optimization problem and present a general nonlinear projection framework that encompasses previous linear projection-based techniques as well as the techniques developed in this dissertation. We illustrate that nonlinear projection is natural and appropriate for reducing nonlinear systems, and can achieve more compact and accurate reduced models than linear projection. The first method, ManiMOR, is a direct implementation of the nonlinear projection framework. It generates a nonlinear reduced model by projection on a general-purpose nonlinear manifold. The proposed manifold can be proven to capture important system dynamics such as DC and AC responses. We develop numerical methods that alleviates the computational cost of the reduced model which is otherwise too expensive to make the reduced order model of any value compared to the full model. The second method, QLMOR, transforms the full model to a canonical QLDAE representation and performs Volterra analysis to derive a reduced model. We develop an algorithm that can mechanically transform a set of nonlinear differential equations to another set of equivalent nonlinear differential equations that involve only quadratic terms of state variables, and therefore it avoids any problem brought by previous Taylor-expansion-based methods. With the QLDAE representation, we develop the corresponding model order reduction algorithm that extends and generalizes previously-developed Volterra-based technique. The third method, NTIM, derives a macromodel that specifically captures timing/phase responses of a nonlinear system. We rigorously define the phase response for a non-autonomous system, and derive the dynamics of the phase response. The macromodel emerges as a scalar, nonlinear time-varying differential equation that can be computed by performing Floquet analysis of the full model. With the theory developed, we also present efficient numerical methods to compute the macromodel. The fourth method, DAE2FSM, considers a slightly different problem -- finite state machine abstraction of continuous dynamical systems. We present an algorithm that learns a Mealy machine from a set of differential equations from its input-output trajectories. The algorithm explores the state space in a smart way so that it can identify the underlying finite state machine using very few information about input-output trajectories.

关键词：降价模型；线性系统；数字电路；算法框架；非线性动态系统

查看摘要 索取原文[201页]

Radios available today are designed to be high performance devices. These radios require careful design by experienced and skilled RF IC designers, more expensive RF processes, and large chip areas for RF passives. The resulting cost of these devices is at the dollar level without the off chip components, and the careful design required makes integration of these radios with other circuits (microprocessors, sensors, etc) an expensive proposition. We believe that radios that require limited design skills while still having good performance will enable widespread use of wireless technologies.

关键词：无线电；发射机；振荡器；微处理器；传感器

查看摘要 索取原文[75页]

Central to this investigation are a pair of models for the phosphorelay, one of which is an Ordinary Differential Equations based model, and the other of which is a Chemical Master Equation based model. The ODE based model is used to rigorously demonstrate that a phosphorelay is monotone, and thus converges to some steady state. In turn, the steady state output is elucidated in terms of the parameters that determine the net influx and net efflux at each stage as well as the growth rate. This steady state output function provides an elaboration on a prior hypothesis which suggests that a long phosphorelay provides additional phosphoregulation targets. Specifically, we find that the output of a phosphorelay is proportional to the net influx rate divided by the sum of various products of efflux signals. In the large efflux signal limit, effluxes are effectively multiplied to generate the final output. In this way, the activity of phosphatases which act on multiple stages in the relay are multiplied, allowing the phosphorelay to act as an analog computation device for this specific function. Growth is shown to have an unexpectedly powerful effect on relay output. In the most extreme cases, the phosphorelay output is shown to obey a power law with respect to growth, with an exponent which can be as large as the length of the relay, and which is also mediated by other key architectural variations. Thus, the phosphorelay can be utilized as a device which allows an organism to select behavior by comparing its growth rate to a threshold, where the level and sharpness of this threshold can be controlled by architectural and parametric changes. These results also provide design laws for building phosphorelays which are robust to growth rate variation.

关键词：生物模块；模拟计算；射流；信息网络

查看摘要 索取原文[80页]

The construction of various of Klein bottles that belong to different regular homotopy classes, and which thus cannot be smoothly transformed into one another, is formally introduced. For all cases it is shown how these shapes can be partitioned into two Mobius bands and how the twistedness of these bands defines the homotopy type.

关键词：定期同伦类；不定向表面

查看摘要 索取原文[21页]

This thesis presents three new computational tools that bring the strength of hybrid dynamical models and optimal control to applications in Cyber-Physical systems. The first tool is an algorithm that nds the optimal control of a switched hybrid dynamical system under state constraints, the second tool is an algorithm that approximates the trajectories of autonomous hybrid dynamical systems, and the third tool is an algorithm that computes the optimal control of a nonlinear dynamical system using pseudospectral approximations. These results achieve several goals. They extend widely used algorithms to new classes of dynamical systems. They also present novel mathematical techniques that can be applied to develop new, computationally efficient, tools in the context of hybrid dynamical systems. More importantly, they enable the use of control theory in new exciting applications, that because of their number of variables or complexity of their models, cannot be addressed using existing tools.

关键词：物理系统；大规模分布式系统；最优控制配方；混合动力系统；控制理论

查看摘要 索取原文[154页]

A multi-stage compilation framework transforms portions of programs written in a productivity-level language into an efficiency-level language, such as C, with explicit hardware-specific optimizations. It is challenging for compiler programmers to debug errors in the compilation because they must perform complicated end-to-end reasoning, relating the programs across the multiple stages of compilation. To simplify this debugging effort, we present multi-level debugging, a novel combination of error-checking algorithms in a multi-stage compilation environment. Our method particularly aims to model and check sequential and parallel notions of nondeterminism and related bugs introduced by the compilation. Using our method, the programmer can systematically eliminate potential sources of the bug in the compilation process and focus only on the real source. We demonstrated on two real multi-stage compilers the effectiveness of multi-stage debugging in simplifying the diagnosis of manually-injected bugs as well as in an actual bug encountered during compiler development.

关键词：编译器程序员；多级并行化；多等级；程序调整

查看摘要 索取原文[12页]

Benefits of technology scaling and the flexibility of digital circuits favor the digital signal processing in many applications, placing additional burden to the analog-to-digital con- verters (ADCs). This has created a need for energy-efficient ADCs in the GHz sampling frequency and moderate effective resolution range. A dominantly digital nature of successive approximation register (SAR) ADCs makes them a good candidate for an energy-efficient and scalable design, but its sequential operation limits its applicability in the GHz sampling range. Time-interleaving can be used to extend the efficiency of the SAR ADCs to the higher frequencies if the mismatches between the interleaved ADC channels can be handled in an efficient manner. New calibration techniques are proposed for time-interleaved SAR ADCs capable of cor- recting the gain, offset and timing mismatches, as well as the static nonlinearities of individ- ual ADC channels stemming from the capacitor mismatches. The techniques are based on introducing two additional calibration channels that are identical to all other time-interleaved channels and the use of the least mean square algorithm (LMS). The calibration of the chan- nel offset and gain mismatches, as well as the capacitor mismatches, is performed in the background using digital post-processing. The timing mismatches between channels are cor- rected using a mixed-signal feedback, where all calculations are performed in the digital do- main, but the actual timing correction is done in the analog domain by fine-tuning the edges of the sampling clocks. These calibration techniques enable a design of time-interleaved con- verters that use minimum-sized capacitors and operate in the thermal-noise-limited regime for maximum energy and area efficiency. The techniques are demonstrated on a time-interleaved converter that interleaves 24 channels designed in a 65nm CMOS technology. The ADC uses the smallest capacitor value of only 50aF, achieves 50.9dB SNDR at fs = 2.8GHz with the effective-resolution bandwidth higher than the Nyquist frequency, while consuming only 44.6 mW of power.

关键词：技术缩放、数字电路、时间交叉特区、校准技术

查看摘要 索取原文[115页]

Our main focus here is on demonstrating properties of LBMPC controllers on the quadrotor testbed, with an implementation of LBMPC that runs in real-time on the quadrotor's on-board computer. Robustness to “mis-learning” is one aspect of LBMPC that we demonstrate in an experiment where we deliberately mis-tune a learning algorithm. We also demonstrate the improvement in performance possible when a well-tuned learning algorithm is used, show learning used to update the model in a physically meaningful way, and demonstrate the use of the LBMPC controller in an integrated robotic task requiring speed and precision: we design a controller that enables the quadrotor to catch balls.

关键词：物理；车载模型；控制器；机器人；四旋翼直升机

查看摘要 索取原文[80页]

The conventional planar bulk MOSFET is difficult to scale down to sub-20nm gate length, due to the worsening performance variability and short channel effects. Thin body transistors, including Multiple-Gate (FinFET & Tri-Gate FET) and Fully Depleted SOI (FD-SOI) MOSFETs are anticipated to replace the current transistor architecture, and will be used in future CMOS technology nodes. Strained Silicon technology is widely used today to boost planar bulk transistor performance. Thus it's technically important to examine the strain-induced performance enhancement in these thin body transistors, for nanometer scale channel length. A comprehensive study on impact of channel stress on ultra-thin-body FD-SOI MOSFETs is presented. It's found that strain-induced mobility enhancement diminishes with Silicon body thickness scaling below 5nm for electrons, but not for holes. Strain-induced carrier transport enhancement is maintained with gate-length scaling. By applying forward back biasing (FBB) through the ultra-thin Buried Oxide layer, both carrier mobilities and their responses to strain get enhanced. For Multiple-gate FETs, the impact of performance enhancement through various types of stressors (including CESL, SiGe Source/Drain, Strained SOI and Metal Gate Last process) is studied, for different fin crystalline orientations and aspect ratios, to provide guidance for 3-D transistor design optimization.

关键词：晶体管；CMOS；诱导性能；场效电晶体

查看摘要 索取原文[104页]

Traditional electrical wiring has become limited in terms of bandwidth capacity and power consumption. As digital circuit elements have reduced in size and increased in speed, electrical interconnects have been struggling to keep up with the bandwidth demands. The primary factors holding back copper wires are high capacitance and inherent dielectric losses. The industry has compensated by placing repeaters and amplifiers along electrical links. However, these methods increase circuit complexity and energy consumption.Phototransistors offer an alternative for low-power optical detection.Others have proposed optical field-effect transistors (FETs) including photo-heterojunction JFETs (photo-hetero-JFETs) [8] and CMOS devices [9]. We will focus on the photo-bipolar junction transistor (photo-BJT) and heterojunction phototransistor (HPT) because of the large current gain of such devices. In Figure 1, the photo-BJT system is compared to the PD receiver system in terms of power consumption and complexity.

关键词：锗化硅；二级晶体管；光学互连

查看摘要 索取原文[26页]