欢迎访问行业研究报告数据库

行业分类

当前位置:首页 > 报告详细信息

找到报告 1 篇 当前为第 1 页 共 1

时间交叉特区A/D转换器的校准技术

Calibration Techniques for Time-Interleaved SAR A/D Converters

作者:Dusan Stepanovic 作者单位:University of California at Berkeley 加工时间:2013-11-20 信息来源:EECS 索取原文[115 页]
关键词:技术缩放、数字电路、时间交叉特区、校准技术
摘 要:Benefits of technology scaling and the flexibility of digital circuits favor the digital signal processing in many applications, placing additional burden to the analog-to-digital con- verters (ADCs). This has created a need for energy-efficient ADCs in the GHz sampling frequency and moderate effective resolution range. A dominantly digital nature of successive approximation register (SAR) ADCs makes them a good candidate for an energy-efficient and scalable design, but its sequential operation limits its applicability in the GHz sampling range. Time-interleaving can be used to extend the efficiency of the SAR ADCs to the higher frequencies if the mismatches between the interleaved ADC channels can be handled in an efficient manner. New calibration techniques are proposed for time-interleaved SAR ADCs capable of cor- recting the gain, offset and timing mismatches, as well as the static nonlinearities of individ- ual ADC channels stemming from the capacitor mismatches. The techniques are based on introducing two additional calibration channels that are identical to all other time-interleaved channels and the use of the least mean square algorithm (LMS). The calibration of the chan- nel offset and gain mismatches, as well as the capacitor mismatches, is performed in the background using digital post-processing. The timing mismatches between channels are cor- rected using a mixed-signal feedback, where all calculations are performed in the digital do- main, but the actual timing correction is done in the analog domain by fine-tuning the edges of the sampling clocks. These calibration techniques enable a design of time-interleaved con- verters that use minimum-sized capacitors and operate in the thermal-noise-limited regime for maximum energy and area efficiency. The techniques are demonstrated on a time-interleaved converter that interleaves 24 channels designed in a 65nm CMOS technology. The ADC uses the smallest capacitor value of only 50aF, achieves 50.9dB SNDR at fs = 2.8GHz with the effective-resolution bandwidth higher than the Nyquist frequency, while consuming only 44.6 mW of power.
© 2016 武汉世讯达文化传播有限责任公司 版权所有 技术支持:武汉中网维优
客服中心

QQ咨询


点击这里给我发消息 客服员


电话咨询


027-87841330


微信公众号




展开客服