Parallel algorithms for sparse matrix-matrix multiplication typically spend most of their time on inter-processor communication rather than on computation, and hardware trends predict the relative cost of communication will only increase. Thus, sparse matrix multiplication algorithms must minimize communication costs in order to scale to large processor counts.

关键词：通信优化；并行算法；稀疏矩阵乘法；通信成本；处理器

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This dissertation proposes a solution to the CMOS power crisis via mechanical computing. Specifically, robust electro-mechanical relay technologies are developed for digital circuit application. A 4-Terminal (4T) relay design is firstly developed. Key technology features include tungsten contacts for high endurance; low-thermal-budget p+-poly-Si0.4Ge0.6 structure for post- CMOS process compatibility; Al2O3 as a reliable insulation material; dry release step to mitigate stiction; and folded-flexure design to mitigate the impact of residual stress. Fabricated relays show good conductance (RON < 10 kΩ), abrupt switching behavior (sub-threshold swing below 0.1 mV/dec), and virtually zero leakage (IOFF ~ 10-14 A). Switching delay in the 100 ns range and endurance exceeding 109 on/off cycles is achieved with excellent device yield (> 95%). With relay design and process optimizations, pull-in voltage below 10 V with less than 1 V hysteresis is achieved. Miniaturization reduces the device footprint to 35μm×50μm, ~10% of the first generation device footprint (120μm×150μm). Relays with multiple source/drain electrodes and multiple gate electrodes are proposed for increased circuit functionality and reduced device count.

关键词：集成电路；数字电路；CMOS；继电器

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As memory accesses increasingly limit the overall performance of reconfigurable accelerators, it is important for high-level synthesis (HLS) flows to adopt a systematic way to discover and exploit memory-level parallelism. This work develops 1) a framework where parallelism between memory accesses can be revealed from runtime profiles of applications and provided to a high level synthesis flow, and 2) a novel multiaccelerator/multi-cache architecture to support parallel memory accesses, taking advantage of the high aggregated memory bandwidth found in modern FPGA devices. Our experimental results have shown that for 10 accelerators generated from 9 benchmark applications, circuits using our proposed memory structure achieve on average 51% improved performance over accelerators using a traditional memory interface. We believe that our study represents a solid advance towards achieving memory-parallel embedded computing on hybrid CPU+FPGA platforms.

关键词：内存；加速器；可重构

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This thesis sprung up from the interest to immerse myself in the inner-workings of the wireless sensor networks (WSNs) that I was deploying as part of my Ph.D. dissertation in Civil Engineering.

关键词：频率信道；无线传感器网络（WSN）；信道跳频；时间同步

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Cyclops (cyclic-operations) Tensor Framework (CTF) 1 is a distributed library for tensor contractions. CTF aims to scale high-dimensional tensor contractions such as those required in the Coupled Cluster (CC) electronic structure method to massively-parallel supercomputers. The framework preserves tensor structure by subdividing tensors cyclically, producing a regular parallel decomposition. An internal virtualization layer provides completely general mapping support while maintaining ideal load balance. The mapping framework decides on the best mapping for each tensor contraction at run-time via explicit calculations of memory usage and communication volume. CTF employs a general redistribution kernel, which transposes tensors of any dimension between arbitrary distributed layouts, yet touches each piece of data only once. Sequential symmetric contractions are reduced to matrix multiplication calls via tensor index transpositions and partial unpacking. The user-level interface elegantly expresses arbitrary-dimensional generalized tensor contractions in the form of a domain specific language. We demonstrate performance of CC with single and double excitations on 8192 nodes of Blue Gene/Q and show that CTF outperforms NWChem on Cray XE6 supercomputers for benchmarked systems.

关键词：并行收缩；计算机内存；内核

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In recent years, resistive random access memory (RRAM) has gained significant attention as one of the promising candidates for next generation memory applications. This is due to its anticipated advantages versus Flash technology with respect to high density, low power and fast read and write speed. The main operation mechanism of these devices is a resistance change induced by filament formation through metal-cations or oxygen vacancies.

关键词：电阻；内存；RRAM

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In this work, we present a succinct derivation for the Square-Root model based on an explicit model from optimal control theory. Our derivation is intuitive and exact, makes fewer assumptions, and requires far fewer steps than the two-submovement derivation presented in Meyer et al. [MAK+88]. To compare the Square-Root model with statistical signi cance, we performed two extensive experiments with homogeneous and heterogeneous targets that appear in sequence on a plane. Later, we extend the two-parameter model to a more accurate three-parameter that increases the accuracy of the model over the two-parameter formulation. The succinct and intuitive derivation and new experimental results may enhance the appeal of the Square-Root model for design of systems and interfaces with heterogeneous targets.

关键词：平方根模型；异构系统；接口

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This thesis mainly explores two fully integrated terahertz transceivers for sensing and communication applications in well matured 0.13 μm BiCMOS and 65 nm digital CMOS technology. Since antenna size shrinks quadratically as radiation frequency increases for a given gain, on-chip antennas have great potential in terahertz range by eliminating packaging issues for cost-effective, compact terahertz transceivers.

关键词：传感和通信；硅设备；太赫兹收发器

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Increasing process variability limits energy reduction in SRAM design by increasing the need for margining and preventing optimal supply voltage scaling. However, tolerating variability with resilient designs can prevent these limitations and enable future energy-efficiency improvements. Understanding resiliency requires understanding how design decisions affect error rates—therefore we propose a unified analytical framework for SRAM design that uses importance sampling of dynamic failure metrics to quantify the effect of different assist techniques, array organization, and timing on failure rates of a 28nm arrays at design-time.

关键词：节能；弹性；SRAM

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报告包括2013年11月上半月通信行业的政策监管、行业要闻、区域要闻、企业要闻、海外要闻。

关键词：通信；政策；运营商；垃圾短信；软件；智能交通；大数据

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