Chip-scale packaging (CSP) emerged in 1990s. Wafer-level CSPs emerged by 1998 and gained popularity due to their low-cost benefits in applications, ranging from application-specific integrated circuits (ASICs) and microprocessors to electrically erasable programmable read-only memories (EEPROMs). The major benefit of WLP is that the wafer fabrication and testing are done on the wafer itself, reducing the cost of WLP with increasing wafer size and decreasing die size.

PART 01: Executive summary

PART 02: Scope of the report

PART 03: Research Methodology

PART 04: Introduction

Key market highlights

PART 05: Technology landscape

Semiconductor IC manufacturing process

WLP versus die-level packaging and assembly

Roadmap of semiconductor packaging industry

Ecosystem of semiconductor IC packaging industry

PART 06: Market landscape

Market size and forecast

Five forces analysis

PART 07: Market segmentation by application

Global FOWLP market by application

Analog and mixed IC

Wireless connectivity

Logic and memory IC

MEMS and sensors

CMOS image sensors

PART 08: Geographical segmentation

APAC

Americas

Europe

PART 09: Decision framework

PART 10: Drivers and challenges

Market drivers

Impact of drivers on key customer segments

Market challenges

Impact of challenges on key customer segments

PART 11: Market trends

Increase in wafer size

High adoption of semiconductor ICs in automobiles

Short replacement cycle of mobile devices

PART 12: Vendor landscape

Competitive scenario

Key vendors

Other prominent vendors

PART 13: Appendix

List of abbreviations

PART 14: Explore Technavio