关键词：平交路口能耗；芯片面积；测量精度
摘 要：In this paper one convetional and two novel designs of 4-bit LCADCs are presented and simulated. The performance of these three circuits are estimated using CadenceVirtuoso?circuit simulation software to model the circuits at the transistor level. The three circuits are then compared in terms of timing accuracy, reference voltage accuracy, total power consumed, and total required area. The proposed integrator LCADC was found to have the lowest power consumption and the least error over one cycle but accumulated error over time. The proposed track and hold LCADC had slightly more timing error and power consumption, but it did not accumulate error and required significantly less area. Therefore the track and hold LCADC was chosen as the best implementation of the three studied in this paper.