关键词：异步电路；CMOS；节能计算
摘 要：This research focuses on the design and implementation of robust and energy-efficient computation architectures by employing an asynchronous self-timed design methodology. A statistical framework is first presented to analyze the energy and delay of CMOS digital circuits considering a variety of timing methodologies. The proposed analysis framework combines variability and statistical performance models, which enables designers to efficiently evaluate circuit performance, and determine the optimal timing strategy, pipeline depth and supply voltage in the presence of variability.