关键词：存储器扩展；静态存储器；晶体管
摘 要：Continued planar bulk MOSFET scaling is becoming increasingly difficult due toincreased random variation in transistor performance with decreasing gate length, andthereby scaling of SRAM using minimum-size transistors is further challenging. Thisdissertation will discuss various advanced MOSFET designs and their benefits forextending density and voltage scaling of static memory (SRAM) arrays. Using threedimensional (3-D) process and design simulations, transistor designs are optimized. Then,using an analytical compact model calibrated to the simulated transistor current-vs.-voltagecharacteristics, the performance and yield of six-transistor (6-T) SRAM cells are estimated.For a given cell area, fully depleted silicon-on-insulator (FD-SOI) MOSFET technology isprojected to provide for significantly improved yield across a wide range of operatingvoltages, as compared with conventional planar bulk CMOS technology. Quasi-Planar (QP)bulk silicon MOSFETs are a lower-cost alternative and also can provide for improvedSRAM yield. A more printable "notchless" QP bulk SRAM cell layout is proposed to reduce lithographic variations, and is projected to achieve six-sigma yield (required forterabit-scale SRAM arrays) with a minimum operating voltage below 1 Volt.