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基于FPGA的高速并行卷积的编码器的设计

The Design of High speed and parallel convolutional encoder Based on FPGA

作者:Liu Yan-yan;Gao Yin-han;Chen Guang-qiu;Wang En-guo 作者单位:College of Instrumentation and Electrical Engineering,Jilin University,Changchun 130061,China;School of Electronic and Information Engineering,Changchun University of Science and Technology,Changchun 加工时间:2015-07-22 信息来源:科技报告(DE) 索取原文[5 页]
关键词:汽车;卷积码;网格图;编码效率; FPGA
摘 要:For the channel source of large capacity image data,the error correcting capability and coding efficiency of channel encoding is very important,in order to solve the real-time and parallel of encoding,a kind of code encoding method realized easily by FPGA is proposed.First,the coding principle of the convolutional code is introduced in detail; Secondly,the representation method of the convolutional encoder is elaborated,including the state transition diagram and the grid diagram of the convolutional code; Then,the convolutional encoding algorithm based on FPGA will be converting to achieve rapid,parallel processing method; Finally,(2,1,7) convolutional code algorithm is simulated and tested.The experimental results show that:the convolutionai encoding module is capable of handling the input data stream of up to 160Mbps,processing speed,to meet the parallel and real-time of convolutional encoding for the channel source of large capacity image data,to improve the efficiency ofconvolutional encoding.
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