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6英寸晶圆上的0.35米CMOS工艺:新马维尔纳米实验室第一个基线运行(基准报告8)

0.35 m CMOS Process on Six-Inch Wafers: The First Baseline Run in the New Marvell NanoLab,  Baseline Report VIII.

作者:A. Sz?cs 作者单位:University of California at Berkeley 加工时间:2013-11-18 信息来源:EECS 索取原文[34 页]
关键词:晶片;晶圆;CMOS
摘 要:This report presents details of the eighth six-inch baseline run, CMOS200, where a moderately complex 0.35 μm twin-well, silicided, LOCOS process was implemented. This process was based on the previous 0.35 μm six-inch run, CMOS192. CMOS200 was the start-up run in the new Marvell NanoLab, showing the ability to fabricate operational MOSFETs, after the move from the Microlab.
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