关键词：Verilog HDL语言;多种功能;硬件描述语言
摘 要：Verilog is the most widely used hardware description language.It can be used in the modeling,synthesis,and simulation stages of the hardware system designing.This thesis is about applying Verilog HDL to design the multifunctional electronic timing system.This system has brought about the timing function,the Alarm clock function,the time checking module,the stop clock module,the exact hour alarming module,the alarm clock's shielding and alarming function module and the stop clock Prompting function module.The modules which have applied this design can be transplanted to other kinds of electronic control systems conveniently.This system uses the Verilog HDL to design,so it has nothing to do with the craft.It allows us to attain the applicable actual circuit easily without considering much about the details of the gate level and the realization of the craft in the function designing stage and the logic verification stage.We just need to exert different conditions according to the demand of the design of the system.