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基于FPGA的执行解码器的有效准循环LDPC码

Implementation of Decoder for effective Quasi-Cyclic LDPC codes Based on FPGA
作者:Jiqu HanLi Liu 加工时间:2014-09-24 信息来源:科技报告(Other) 索取原文[5 页]
关键词:近似下三角结构的LDPC;失调基于BP译码算法; FPGA
摘 要:Designers are increasingly relying on FPGA-based emulation to evaluate the performance of LDPC codes.In this paper,we propose a novel approximate lower triangular structure for the parity part of the parity-check matrix of QC-LDPC codes.Next,a high speed partially parallel decoder architecture which based on the Offset BP-based decoding algorithm is proposed.The results indicate that the frequency can reach 100MHz and its throughput rate can reach 113Mbps.
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