关键词：集成电路；数字电路；CMOS；继电器
摘 要：This dissertation proposes a solution to the CMOS power crisis via mechanical computing. Specifically, robust electro-mechanical relay technologies are developed for digital circuit application. A 4-Terminal (4T) relay design is firstly developed. Key technology features include tungsten contacts for high endurance; low-thermal-budget p+-poly-Si0.4Ge0.6 structure for post- CMOS process compatibility; Al2O3 as a reliable insulation material; dry release step to mitigate stiction; and folded-flexure design to mitigate the impact of residual stress. Fabricated relays show good conductance (RON < 10 kΩ), abrupt switching behavior (sub-threshold swing below 0.1 mV/dec), and virtually zero leakage (IOFF ~ 10-14 A). Switching delay in the 100 ns range and endurance exceeding 109 on/off cycles is achieved with excellent device yield (> 95%). With relay design and process optimizations, pull-in voltage below 10 V with less than 1 V hysteresis is achieved. Miniaturization reduces the device footprint to 35μm×50μm, ~10% of the first generation device footprint (120μm×150μm). Relays with multiple source/drain electrodes and multiple gate electrodes are proposed for increased circuit functionality and reduced device count.