关键词：晶体管；阈值电压；模拟电路；静态存储器
摘 要：As transistor dimensions are scaled down in accordance with Moore’s Law to provide for improved performance and cost per function, variability in transistor performance grows in significance and can present a major challenge for achieving high yield in the manufacture of integrated circuits utilizing transistors with sub-30 nm gate lengths. Increased variability in the threshold voltage (VT) of a transistor ultimately limits the minimum operating voltage for six transistor (6T) static memory (SRAM) cells, hinders aggressive scaling of cell area, and causes performance degradation in analog circuits. Better understanding and accurate assessment of device variation are needed in order to minimize yield loss and design margin.