关键词：FPGA；ASIC 设计；工具流
摘 要：In this work, we designed and implemented an open source FPGA with tool flow support. We named the project Archipelago and designed the architecture with two goals. First, it explores the quality of the physical implementation result that is produced by a standard ASIC design flow in a modern ASIC process. Second, it enables other people to use and extend the project at will. The outcome of this project is a parameterizable and user expandable FPGA with toolflow support. We verified its functionality. The performance of the work is good enough for real world work loads. A 64 Bit counter can run up to 364MHz on average on three different FPGA instances. The result is comparable to a commercial FPGA implemented in a similar process technology.